DS1225Y DATASHEET PDF

SEMICONDUCTOR. DSY. 64K Nonvolatile SRAM. PIN ASSIGNMENT. FEATURES. 10 years minimum data retention in the absence of external power. CC. DSY Datasheet, DSY 64k Nonvolatile SRAM Datasheet, buy DSY DSY datasheet, DSY pdf, DSY data sheet, datasheet, data sheet, pdf, Dallas Semiconductor, 64K Nonvolatile SRAM.

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When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. The unique address specified by the 13 address inputs A0-A12 defines which of the bytes of daasheet is to be accessed.

Maxim Integrated DSY+ – PDF Datasheet – RAM In Stock |

Valid data will be available to the eight data output drivers within tACC Access Time after the last address input signal is stable, providing that CE and OE access times are also satisfied. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE.

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All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time tWR before another cycle can be initiated.

The OE control signal should be kept inactive high during write cycles to avoid bus contention. Data is maintained in the absence of VCC without any additional support circuitry.

As VCC falls below approximately 3. During power-up, when VCC rises above approximately 3. Storage Temperature Lead Temperature soldering, 10s Note: EDIP is wave or hand soldered only.

DS1225Y-150IND

fs1225y Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.

WE is high for a read cycle. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output buffers remain in a high-impedance state during this period.

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If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period.

AA designates the year of manufacture. BB designates the week of manufacture. datwsheet

DSY Datasheet pdf – 64K Nonvolatile SRAM – Dallas Semiconductor

The expected tDR is defined as starting at the date of manufacture. All AC and DC electrical characteristics are valid over the full operating temperature range. In a power down condition the voltage on any pin may not exceed the voltage on VCC. All voltages are referenced to ground.

Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.